Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary.
Researchers at QuTech, Delft University of Technology, have combined flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. They further showed an example of performing the Steane code error correction on two current superconducting processors and numerically analyzed their performance with circuit level noise. The simulation results showed that the QEC circuits that measured more stabilizers in parallel had lower logical error rates. They also observed that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, the team has foreseen potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques. (QuTech)
