P-computers are powered by probabilistic bits (p-bits), which interact with other p-bits in the same system. Unlike the bits in classical computers, which are in a 0 or a 1 state, or qubits, which can be in more than one state at a time, p-bits fluctuate between positions and operate at room temperature.
Researchers at UC Santa Barbara achieved promising results by using classical hardware to create domain-specific architectures. They developed a unique sparse Ising machine (sIm), a novel computing device used to solve optimization problems and minimize energy consumption.
The team’s prototyped architecture included a field-programmable gate array (FPGA), a powerful piece of hardware that provides much more flexibility than application-specific integrated circuits.
The researchers showed that their sparse architecture in FPGAs was up to six orders of magnitude faster and had increased sampling speed five to eighteen times faster than those achieved by optimized algorithms used on classical computers.
In addition, they reported that their sIm achieves massive parallelism where the flips per second — the key figure that measures how quickly a p-computer can make an intelligent decision — scales linearly with the number of p-bits.
The paper has been published in Nature Electronics.
